Embedded non-volatile memory device and fabrication method of the same

ABSTRACT

Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.

CROSS-REFERENCE TO RELATED APPLICATIONS

This present application is a continuation of U.S. Non-Provisionalapplication Ser. No. 15/848,439, filed on Dec. 20, 2017, which claimsthe priority and benefit of U.S. Provisional Application No. 62/534,512filed on Jul. 19, 2017, the entire contents of which are herebyincorporated by reference.

BACKGROUND

Non-volatile memory (NVM) cells, such as flash memory cells, store datain computer memory systems. NVM cells may be formed on semiconductorsubstrates and include a number of transistors to provide memoryfunctions and logic functions.

BRIEF DESCRIPTION OF THE DRAWINGS

The described embodiments and the advantages thereof may best beunderstood by reference to the following description taken inconjunction with the accompanying drawings. These drawings in no waylimit any changes in form and detail that may be made to the describedembodiments by one skilled in the art without departing from the spiritand scope of the described embodiments.

FIG. 1 is a diagram of an example integrated split-gate non-volatilememory cell, according to some aspects of the disclosure.

FIG. 2 is an example embedded split-gate NVM device during a portion offabrication of the device, according to some aspects of the disclosure.

FIG. 3 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 4 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 5 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 6 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 7 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 8 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 9 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 10 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 11 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 12 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 13 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 14 is an example embedded split-gate NVM device during anotherportion of fabrication of the device, according to some aspects of thedisclosure.

FIG. 15 is a flow chart showing an example method for fabricating asplit-gate NVM device, according to some aspects of the disclosure.

FIG. 16 is a flow chart showing an example method for fabricating asplit-gate NVM device, according to some aspects of the disclosure.

DETAILED DESCRIPTION

A split-gate non-volatile memory (NVM) cell can include a memory gateand a select gate formed on a semiconductor substrate. The split-gateconfiguration may provide improved size and efficiency characteristicscompared to one transistor or two transistor NVM cell configurations. Asplit-gate memory cell may include a select gate to enable access todata stored in the memory cell and a memory gate that stores the data.In some implementations, the select gate and memory gate may beseparated on a semiconductor substrate by one or more inter-gatedielectric layers.

While split-gate memory cells may provide some advantages in certaindevices, integrating split-gate memory cells on a semiconductorsubstrate with certain logic devices may cause difficulties infabrication. For example, certain advanced logic processes may use ahigh dielectric constant (high-k) gate dielectric with a metal gate(HKMG) to improve transistor performance and reduce leakage current.Some example high-k materials may include Hafnium Dioxide, ZirconiumDioxide, Titanium Dioxide, or the like. In some implementations, thehigh-K material may be characterized as having a dielectric constantgreater than 2, 3, 3.5, or another value to provide proper functioningof the gate while reducing leakage currents. The HKMG may be fabricatedusing high-k dielectric material instead of a silicon based gatedielectric, such as silicon dioxide. In some implementations, however,fabrication of HKMG logic gates on the same substrate as a split-gatememory cell may cause shifts in the properties of the logic transistor.Additionally, differences in heights of a split-gate memory cell and alogic transistor may prevent proper fabrication of the memory cell orlogic transistors during certain processing steps.

Disclosed herein are semiconductor devices and processes to integrate asplit-gate NVM cell with a HKMG. The embedded devices may include asemiconductor substrate, such as Silicon, in a memory cell region of thesubstrate that is about the same height as the semiconductor substratein a logic region of the device. For example, the substrate height inthe different regions may be within approximately 200 angstroms of oneanother. The embedded device may also include upper surfaces of memorygates and select gates in the split-gate memory cell that aresubstantially co-planar. For example, the upper surface of the selectgate and memory gate may be within approximately 300 angstroms of oneanother. Similarly, the upper surfaces of the select gate and memorygate may also be substantially co-planar with the upper surface of theHKMG logic transistor. This may reduce interference during logic gatereplacement portions of a fabrication process. In some implementations,a silicide may also be formed on portions of the select gate or memorygate of a split-gate memory cell while silicide is not formed on adielectric that separates the select gate and the memory gate.

Processes for fabricating a split-gate NVM cell embedded with an HKMGlogic transistor may include fabricating the split-gate memory cell in afirst region of a semiconductor substrate and a field-effect transistor(FET) with a high-k metal gate in a second region of the semiconductorsubstrate. Forming the split-gate memory cell may include forming aselect gate (SG) and a memory gate (MG) adjacent to the select gate. Insome implementations, the SG and MG may be separated by one or morelayers of a dielectric. The logic FET may be formed on the samesemiconductor substrate with a polysilicon gate, which may then bereplaced with a metal gate. The high-k metal gate (HKMG) FET and thesplit-gate NVM memory cell may thus be formed on a semiconductorsubstrate having a substantially coplanar upper surface. Accordingly, insome embodiments, the semiconductor substrate may be substantially ofsimilar thickness in both regions. For example, the SG, MG, and FET maybe formed without creating a cavity or a recess in the substrate priorto deposition of elements of the gates. Furthermore, the heights of theSG, MG, and FET may be configured such that top surfaces of each of theSG, MG, and FET are substantially co-planar. Additional details ofprocessing to fabricate the embedded split-gate memory device with ahigh-K metal gate FET are described in details with reference to theFigures below.

FIG. 1 is a block diagram of an example split-gate NVM cell 100. Asshown in FIG. 1, the split-gate NVM cell 100 may include a select gate110 and a memory gate 120. The select gate 110 and memory gate 120 areformed on a semiconductor substrate 130. For example, the semiconductorsubstrate 130 may be silicon wafer or other substrate material. Asshown, the select gate 110 and the memory gate 120 are formed on thesubstrate 130 without forming a recess in the semiconductor.Accordingly, the semiconductor substrate 130 has a substantially planartopography around the areas where the select gate 110 and the memorygate 120 are formed. A dielectric layer 140 may also be formed on thesemiconductor substrate 130 to separate the select gate 110 and thememory gate 120. In some implementations, dielectric layer 140 mayinclude multiple layers of dielectric materials.

The split-gate memory cell 100 as described with reference to FIG. 1 mayinclude additional components and features than are shown. The examplesplit-gate memory cell 100 is meant to show particular features of thememory cell to describe the configuration, and additional components maybe used within the memory cell or in the periphery of the memory cell toperform operations. For example, the memory cells as described furtherbelow are embedded in a semiconductor device with a high-k metal-gate(HKMG) logic FET. The memory cells as described below also includeadditional details of the MG 110 and SG 120.

When implemented in a semiconductor device, a number of split-gatedevices 100 may be formed in a memory array. The memory array may beaccessed with control circuitry to address particular memory cells. Forexample, row decoders and column decoders may be used to address memorycells based on a command received at control circuitry. Furthermore,sense amplifiers and word line or bit line drivers may be used to applycurrent to an addressed split-gate memory device and sense data storedin a memory gate 110 of the device.

FIG. 2 is a diagram of an example embedded split-gate NVM device 200during a portion of fabrication of the device. In FIG. 2, the basis ofthe embedded split-gate NVM device 200 is formed on a semiconductorsubstrate 220. For example, an oxide-nitride-oxide (ONO) stack 210 maybe formed at least in a memory region 225 of the semiconductor substrate230. In some implementations, the ONO stack 210 may be formed both inthe memory region 225 and periphery region or a logic FET region 227,and later removed from the periphery region and the logic FET region. Insome implementations, other structures than an oxide-nitride-oxide maybe formed on the semiconductor substrate. For example, theoxide-nitride-oxide stack 210 may further be formed with a top andbottom silicon layer in some implementations.

The semiconductor substrate 220 may also include a logic FET region 227that is separate from the memory region 225. In one embodiment, memoryand logic FET regions 225 and 227 may be disposed adjacent to oneanother. In other embodiments, they may be disposed in different partsof the single semiconductor substrate 220. For example, the logic FETregion 227 may be formed later in fabrication to include a high-k metalgate FET or other control circuitry for accessing memory cells in thememory region 225. In some implementations, the logic FET region 227 mayalso include other components or features in addition to a high-k metalgate FET. In one embodiment, semiconductor substrate 220 may have arelatively flat surface both in the memory region 225 and the logic FETregion 227. The substrate 220 surfaces in the memory region and thelogic FET region 227 are substantially co-planar, or are within 200Angstrom of co-planar of one another.

In some implementations a memory gate polysilicon film 230 may bedeposited on top of the oxide-nitride-oxide stack 210. As shown, thememory gate polysilicon film 230 may be deposited across the surface ofthe semiconductor substrate 220 including the logic FET region 227 andthe memory region 225. A dielectric film 240 may be deposited on top ofthe memory gate polysilicon film 230 to act as a cap layer for thememory gate. In some implementations, the dielectric film may be about20 Angstrom to about 500 Angstrom thick. In some implementations, asecond polysilicon film 250 may also be deposited on top of thedielectric film 240 as an additional portion of the cap layer.

FIG. 3 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 3, thememory gate polysilicon film 230, dielectric film 240 and optionalsecond polysilicon layer 250 have been patterned to the shape of memorygates 260. For example, the device 200 may have had a mask (not shown inFIG. 3) applied to form a pattern using lithography. The mask mayprotect portions of the memory gate polysilicon film 230 while etchingis performed on the device 200. Depending on the implementation, theetching may be a wet etch, a dry etch, or a combination of wet etchingand dry etching. The etching process may remove portions of the memorygate polysilicon film 230 that are not protected by the mask. Theremaining portions of the memory gate polysilicon film 230 may form thememory gates 260. In some implementations, the memory gates 260 may beformed or patterned on a semiconductor substrate 220 in a differentmanner than lithography patterning and etching. In one embodiment, theetching process may stop at the bottom oxide layer of the ONO stack 210in the memory region 225, or another layer.

FIG. 4 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 4, adielectric film 270 is deposited at least on the two lateral sides ofthe memory gates 260. The dielectric film 270 may eventually be formedas an inter-gate dielectric to separate the memory gates 260 from thelater formed select gates in the split-gate memory device 200. In someimplementations, the dielectric film 270 may include multiple layers ofpotentially different dielectric materials. For example, the dielectricfilm 270 may be formed by multiple deposition or oxidation processes toapply different dielectrics to the sides of the memory gates 260. Thedielectric film 270 may also be applied to materials in the logic FETregion 270 of the semiconductor substrate 220. In one embodiment, thedielectric film 270 includes at least two dielectric layers.

FIG. 5 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 5, a selectgate polysilicon film 280 is deposited on the split-gate memory device200. The select gate polysilicon film 280 may be deposited across thesemiconductor substrate 220 including the memory region 225 and thelogic FET region 227. In some implementations, the select gatepolysilicon film 280 may be similar to the memory gate polysilicon film250 described above. For example, in some embodiments, the select gatepolysilicon film and the memory gate polysilicon film may each beun-doped polysilicon films. In some embodiments, one or both of thememory gate polysilicon film 230 or the select gate polysilicon film 280may be a doped polysilicon film. In the case that either of thepolysilicon films 230 or 280 is deposited un-doped, it may be doped withn-type or p-type dopants at a later stage of processing. In someimplementations, the select gate polysilicon film 280 may be doped in adifferent manner than the memory gate polysilicon film 230 to providedifferent electrical characteristics. A select gate dielectric may alsobe formed underneath and before the select gate polysilicon film 280 isdeposited.

FIG. 6 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 6 portionsof the select gate polysilicon film 280 have been removed from thesplit-gate NVM device 200. For example, portions of the select gatepolysilicon film 280 may be removed using a planarizing process. Inaddition, if the optional second polysilicon layer 250 was appliedpreviously, portions of it may be removed during the planarizingprocess. In some implementations, a chemical-mechanical planarization(CMP) process may be used to planarize the layers including the selectgate polysilicon film 280 and the optional second polysilicon layer 250.For example, in some embodiments, the CMP process may planarize thefilms to a level of the dielectric film 240. As shown the remainingportions of dielectric film 240 on the memory gate polysilicon film 230may cause the remaining memory gate 260 to have a slightly lower topsurface compared to the select gate polysilicon film 280. In someimplementations, other processes may be used to form a flat uppersurface as shown in the FIG. 6. Furthermore, as shown in FIG. 8, theprocess may be applied to both a memory region 225 and a logic FETregion 227. After the CMP process, or other planarizing process, thememory gate 260 and the select gate polysilicon film 280 may have uppersurfaces that are substantially co-planar, or are within 300 Angstrom ofco-planar of one another. In addition, the memory gate stack (memorygate 260 and ONO stack 210) and the select gate stack (select gatepolysilicon film 280 and select gate dielectric) may be of substantiallysimilar height, or within 300 Angstrom of difference in height. In oneembodiment, neither the memory gate stack nor the select gate stack isformed in a recessed portion of the semiconductor substrate 220.

FIG. 7 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 7, formerlyformed layers including the memory gate polysilicon film 230 and theselect gate polysilicon film 280 have been removed from the logic FETregion 227 of the semiconductor substrate 220. In addition, functionalportions of an eventual FET device 290 may be formed in the logic FETregion 227. For example, a FET gate dielectric 292 and sacrificialpolysilicon gate 294 may be formed on the logic FET region 227. In oneembodiment, FET gate dielectric 292 may include high-K materialincluding but not limited to Hafnium Dioxide, Zirconium Dioxide,Titanium Dioxide, or the like. Optionally, a gate hardmask 296 may beformed overlying the sacrificial polysilicon gate 294. The FET device290 may be formed to have a height substantially similar to the heightof the select gate stack and the memory gate stack. In some embodiments,after removal of memory gate polysilicon film 230 from the logic FETregion 227, a high-K gate dielectric layer (that become gate dielectric292) and a sacrificial polysilicon layer (that will become sacrificialpolysilicon gate 294) may be deposited across the logic FET region 227of the semiconductor substrate 220. Those layers may then be patternedand etched to provide a basis of FET device 290 that includes a gatedielectric 292 and a sacrificial polysilicon layer 294. In someembodiments, the FET device 290 may be of similar height of the selectgate polysilicon layer 280 or memory gate 260. In some embodiments, agate hardmask 296 may also be deposited and etched on top of the FETdevice 290.

FIG. 8 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 8, adielectric film 310 is deposited over portions of the memory region 225and the logic FET region 227. The dielectric film 310 may be SiO₂, SiN,SiRN, SiON, or the like. The dielectric layer 310 may act as a hardmaskfor additional etching processes described below. In someimplementations, the dielectric layer 310 may form part of the logic FET290, for example the eventual spacer of logic FET 290. Furthermore, asshown in FIG. 8, the dielectric layer 310 may be patterned to only coverportions of the split-gate memory device 200 using lithography andetching.

FIG. 9 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 9, etchinghas been performed to remove portions of the select gate polysiliconfilm 280 on one lateral side of memory gate 260, such as the source sideof split-gate memory cell. In various embodiments described herein, theetching may be a wet etching, a dry etching process, or a combinationthereof. For example, after the etching process, region 320 may be opento separate different memory gates 260. In some implementations, theregion 320 may be opened using different processes than etching. Theetching may remove portions of the select gate polysilicon film 280 atsource regions of the split-gate memory devices. In one embodiment, awet etch may be used to achieve high etch selectivity between the selectgate polysilicon film 280 and various dielectric films (for example,dielectric film 310). In some implementations, Tetramethylammoniumhydroxide (TMAH) may be used as an exemplary wet etch chemical. Thememory gate 260 and the logic FET 290 may be encapsulated by dielectricmaterial 310 as shown in FIG. 9 to protect portions of select gatepolysilicon film 280, logic FET 290 and the memory gate 260 during theetching process.

FIG. 10 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 10, etchinghas been performed to pattern portions of the select gate polysiliconfilm 280 on another lateral side of memory gate 260, such as the drainside of the split-gate memory cell. As described above, in variousembodiments, the etching may be dry etching or wet etching and may beperformed in different orders than described. The etching may removeadditional portions of the select gate polysilicon film 280 to formpatterned select gates 280 as shown in FIG. 10. In one embodiment, theremoving of select gate polysilicon film 280, as described in FIG. 9,and the patterning of select gate polysilicon film 280 to form selectgate 280, as described in FIG. 10, may be performed concurrently. Inanother embodiment, they may be performed individually. Although shownhaving a memory array having common source lines to be formed betweenadjacent memory gates 260, in some embodiments, a split-gate memoryarrays may be formed with memory cells having select gates 280 on eithersides of memory gates 260 throughout. In such cases, the formation ofmemory gates 260 and select gates 280 may be formed using the techniquesdescribed herein, but with different patterning of dielectric film 310for particular polysilicon layers.

FIG. 11 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. Logic FET spacers340 and split-gate source or drain spacers 330 are formed on thesemiconductor substrate 220. Logic FET spacers 340 and split-gate sourceor drain spacers 330 may be formed concurrently or individually. In oneembodiment, source and drain implants (not shown in this figure), suchas lightly doped drain (LDD) or source/drain implants, may be formed insubstrate 220 besides or underneath logic FET spacers 340 and split-gatesource or drain spacers 330.

FIG. 12 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 12,silicide 350 is formed overlaying source and drain regions of logic FET290 and split-gate memory devices. In one embodiment, silicide 350 isformed on an upper surface of select gates 280. In some implementations,the silicide 350 may be formed on an upper surface of the memory gates260 instead of or in addition to being formed on the select gates 280.Furthermore, silicide formation may be prevented in regions between theselect gates 280 and the memory gates 260 by a dielectric film.

FIG. 13 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 13 aninterlayer dielectric (ILD) has been deposited over and around theselect gates 280, memory gates 260, and logic FET 290. In someembodiments, the ILD layer may be an oxide layer, or it may be adifferent form of dielectric. The ILD layer 360 may subsequently beplanarized to provide a level upper surface between the select gates280, memory gates 260, and the logic FET 290. In some embodiments, a CMPprocess may stop when FET hardmask 296 of the logic FET device 290 isexposed. The CMP process may also proceed to expose the sacrificialpolysilicon gate 294 of the logic FET device 290 instead. In oneembodiment, the CMP process of the ILD layer 360 may configure the uppersurfaces of memory gate 260, select gate 280, and logic FET 290 to besubstantially co-planar, or within 300 Angstrom of co-planar.

FIG. 14 is a diagram of an example embedded split-gate NVM device 200during another portion of fabrication of the device. In FIG. 14, aprotective mask 370 has been applied to memory region 225 of thesplit-gate NVM device 200. In one embodiment, the protective mask 370may include but not limited to, silicon oxide, silicon nitride, orsilicon carbon nitride. The protective mask 370 may protect thesplit-gate memory cells including memory gates 260 and select gates 280.The logic FET region 227 may not be covered by the protective mask 370.For example, the protective mask 370 may be removed from the logic FETregion 227. After masking the memory region 225 of the substrate 220, anetching (dry etching or wet etching) process may be performed to removethe sacrificial polysilicon gate 294 (and any hardmask 296 remaining onthe sacrificial polysilicon gate 294). A metal gate material 380 maythen be deposited overlying FET gate dielectric 292 in the logic FETregion 227 to replace the sacrificial polysilicon gate 294 that waspreviously forming the gate of the FET device 290. After deposition ofthe metal gate material 380, the split-gate memory device 200 may becomplete with select gates 280 and memory gates 260 forming a split-gatememory cell integrated with the high-k metal gate (HKMG) logic FET 390.In one embodiment, metal gate material 380 may include but not limitedto tungsten, aluminum, TiN, TiAl, or other metal metals, alloys, orcomposits. After metal gate material 380 is formed, optionally, a metalpolish process may be performed to planarize an upper surface of theHKMG logic FET 390.

FIG. 15 is a flow chart showing an example method 400 for fabricating asplit-gate NVM device as described above. For example, the method 400may be implemented to fabricate split-gate memory device 200 as shown inFIGS. 2-14 and described above.

Beginning in block 410, a memory gate may be formed in a first region ofa semiconductor substrate. For example, a memory gate may be formed asdescribed with reference to FIGS. 2-4 above by depositing a polysiliconfilm and removing portions of the film using lithography and etching. Insome implementations, the memory gate may be formed in a differentmanner.

In block 420, a logic field-effect transistor is formed in a second(logic FET) region of the semiconductor substrates. The logic FET mayhave a high-K dielectric and is formed temporarily with a polysilicongate. For example, the logic FET may be formed as described withreference to FIG. 7 above.

In block 430, a select gate is formed adjacent to the memory gate in thefirst (memory) region of the semiconductor substrate. For example, theselect gate may be formed by depositing a polysilicon film, etching backthe polysilicon film such that the memory gate and select gate aresubstantially coplanar, and patterning the film to remove portions ofthe select gate. In some implementations, the select gate may be formedas describe above with respect to FIGS. 5-10.

In block 440 the polysilicon gate of the logic FET is replaced with ametal gate. After replacing the metal gate, devices formed in the memoryregion and in the logic FET region may be substantially co-planar. Theheight at which they are coplanar after a CMP process may expose eithera hardmask on the sacrificial polysilicon gate or the sacrificialpolysilicon gate itself. The sacrificial polysilicon gate may then beetched away with either a wet etching or dry etching process afterpatterning of a protective layer to protect the memory region. The metalgate may then be formed where the sacrificial polysilicon gate wasremoved. In some implementations, the metal may replace the polysilicongate as described with reference to FIG. 14 above.

FIG. 16 is a flow chart showing an example method for fabricating asplit-gate NVM device as described above. For example, the method 400may be implemented to fabricate split-gate memory device 200 as shown inFIGS. 2-10 and described above. Beginning in block 510, a polysiliconmemory gate layer may be deposited on a semiconductor substrate on topof a charge-storage film in a first region of the semiconductorsubstrate. The polysilicon memory gate layer is then patterned andetched to form a memory gate. For example, the memory gate may bedeposited and formed as described with reference to FIGS. 2-4 above.

In block 520 a select gate oxide may be formed underneath a polysiliconselect gate layer. For example, the polysilicon select gate layer may bedeposited as described above with reference to FIG. 5. In someimplementations, a select gate may be formed with other components orfeatures than as shown in the figures.

In block 530, the polysilicon select gate layer may be leveled such thattop surface of the polysilicon select gate layer is substantiallycoplanar with the top surface of the memory gate. For example, thepolysilicon select gate layer may be leveled using a CMP process, oranother process for developing a consistent plane on the surface of thedevice. In some implementations, the leveling or planarizing may beperformed as described with reference to FIG. 6 above.

In block 540, the planarized/leveled polysilicon select gate layer maybe etched to remove portions of the polysilicon select gate layerdisposed between two memory gates, for example on a source side of thesplit-gate memory cell. In some implementations, Tetramethylammoniumhydroxide (TMAH) may be used as an exemplary wet etch chemical. Forexample, the wet etching or dry etching may be performed as discussedabove with reference to FIG. 9.

In block 550, additional portions of the polysilicon select gate layermay be removed to form the select gate. In one embodiment, the selectgate may be formed adjacent to the memory gate on a drain side of thesplit-gate memory cell. For example, a polysilicon select gate layer maybe removed with a lithography and etching process, such as dry etchingor wet etching processes. In some implementations, the polysiliconselect gate film may be removed as described with reference to FIG. 10above.

Additionally, some embodiments may be practiced in distributed computingenvironments where the machine-readable medium is stored on and orexecuted by more than one computer system. In addition, the informationtransferred between computer systems may either be pulled or pushedacross the communication medium connecting the computer systems.

Although the operations of the methods herein are shown and described ina particular order, the order of the operations of each method may bealtered so that certain operations may be performed in an inverse orderor so that certain operation may be performed, at least in part,concurrently with other operations. In another embodiment, instructionsor sub-operations of distinct operations may be in an intermittent andor alternating manner. The terms “first,” “second,” “third,” “fourth,”etc. as used herein are meant as labels to distinguish among differentelements and may not necessarily have an ordinal meaning according totheir numerical designation. As used herein, the term “coupled” may meanconnected directly or indirectly through one or more interveningcomponents. Any of the signals provided over various buses describedherein may be time multiplexed with other signals and provided over oneor more common on-die buses. Additionally, the interconnection andinterfaces between circuit components or blocks may be shown as buses oras single signal lines. Each of the buses may alternatively be one ormore single signal lines and each of the single signal lines mayalternatively be buses.

The above description sets forth numerous specific details such asexamples of specific systems, components, methods, and so forth, inorder to provide an understanding of several embodiments of the presentinvention. It may be apparent to one skilled in the art, however, thatat least some embodiments of the present invention may be practicedwithout these specific details. In other instances, well-knowncomponents or methods are not described in detail or are presented insimple block diagram format in order to avoid unnecessarily obscuringthe present invention. Thus, the specific details set forth are merelyexemplary. Particular implementations may vary from these exemplarydetails and still be contemplated to be within the scope of the presentinvention.

Embodiments of the claimed subject matter include, but are not limitedto, various operations described herein. These operations may beperformed by hardware components, software, firmware, or a combinationthereof.

The above description sets forth numerous specific details such asexamples of specific systems, components, methods, and so forth, inorder to provide an understanding of several embodiments of the claimedsubject matter. It may be apparent to one skilled in the art, however,that at least some embodiments of the may be practiced without thesespecific details. In other instances, well-known components or methodsare not described in detail or are presented in simple block diagramformat. Thus, the specific details set forth are merely exemplary.Particular implementations may vary from these exemplary details andstill be contemplated to be within the scope of the claimed subjectmatter.

1-20. (canceled)
 21. A semiconductor device, comprising: a memory cellin a first region of a substrate, the memory cell including apolysilicon memory gate (MG) overlying a charge trapping layer; and alogic field-effect transistor (FET) including a metal gate disposed overa high-k dielectric in a second region of the substrate, wherein the MGof the memory cell and the metal gate of the logic FET havesubstantially a same height.
 22. The semiconductor device of claim 21wherein the memory cell is a split-gate memory cell further comprising apolysilicon select gate (SG) overlying a SG oxide layer, the SG formedadjacent to the MG and separated therefrom by an inter-gate dielectric.23. The semiconductor device of claim 22 wherein top surfaces of the MG,the SG and the metal gate of the logic FET are substantially co-planar.24. The semiconductor device of claim 23 wherein a first surface of thesubstrate in the first region and a second surface of the substrate inthe second region of the substrate are substantially co-planar.
 25. Thesemiconductor device of claim 23 wherein the inter-gate dielectricextends from the SG oxide layer to the top surfaces of the MG and theSG.
 26. The semiconductor device of claim 23 wherein the top surface ofat least one of the MG and the SG is silicided.
 27. The semiconductordevice of claim 23 wherein the top surfaces of the MG and the SG aresilicided, and wherein no silicide lies above the inter-gate dielectricthat separates the SG and the MG.
 28. The semiconductor device of claim22 further comprising an inter-layer dielectric (ILD) formed over thesubstrate surrounding the MG, the SG and the metal gate of the logicFET, the ILD planarized to have a top surface substantially co-planarwith the top surfaces of the MG, the SG and the metal gate of the logicFET.
 29. The semiconductor device of claim 22 wherein the chargetrapping layer is a multi-layer charge trapping layer comprising anoxide-nitride-oxide (ONO) stack, and wherein a lower oxide of the ONOstack is formed from an oxide layer that is contiguous with the SG oxidelayer.
 30. A semiconductor device, comprising: a plurality of split-gatememory cells in a memory region of a substrate, each split gate memorycell including a polysilicon memory gate (MG) overlying a chargetrapping layer, and a polysilicon select gate (SG) overlying a SG oxidelayer formed adjacent to the MG and separated therefrom by an inter-gatedielectric; and a plurality of logic field-effect transistor (FET) in alogic region of the substrate, each logic FET including a metal gatedisposed over a high-k dielectric, wherein top surfaces of each of theMGs, the SGs and the metal gate of the logic FETs are substantiallyco-planar.
 31. The semiconductor device of claim 30 wherein theinter-gate dielectric in each split gate memory cell extends from the SGoxide layer to the top surfaces of the MG and the SG.
 32. Thesemiconductor device of claim 30 wherein the top surfaces of each of theMG and the SG are silicided, and wherein no silicide lies above theinter-gate dielectric that separates the SG and the MG in at least oneof the split-gate memory cell.
 33. The semiconductor device of claim 30further comprising an inter-layer dielectric (ILD) formed over thesubstrate surrounding the MGs, the SGs and the metal gate of the logicFETs, the ILD planarized to have a top surface substantially co-planarwith the top surfaces of the MGs, the SGs and the metal gate of thelogic FETs.
 34. The semiconductor device of claim 30 wherein the chargetrapping layer in each split gate memory cell is a multi-layer chargetrapping layer comprising an oxide-nitride-oxide (ONO) stack, andwherein a lower oxide of the ONO stack is formed from an oxide layerthat is contiguous with the SG oxide layer.
 35. A semiconductor device,comprising: a memory array including a plurality of split-gate devicesin a memory region of a substrate, each split-gate device including apolysilicon memory gate (MG) overlying a charge trapping layer, and apolysilicon select gate (SG) overlying a SG oxide layer formed adjacentto the MG and separated therefrom by an inter-gate dielectric; andcontrol circuitry including a plurality of logic field-effect transistor(FET) in a logic region of the substrate, each logic FET including ametal gate disposed over a high-k dielectric, wherein top surfaces ofeach of the MGs, the SGs and the metal gate of the logic FETs aresubstantially co-planar.
 36. The semiconductor device of claim 35wherein the inter-gate dielectric in each split gate memory cell extendsfrom the SG oxide layer to the top surfaces of the MG and the SG. 37.The semiconductor device of claim 35 wherein the top surfaces of each ofthe MG and the SG are silicided, and wherein no silicide lies above theinter-gate dielectric that separates the SG and the MG in eachsplit-gate memory cell.
 38. The semiconductor device of claim 35 furthercomprising an inter-layer dielectric (ILD) formed over the substratesurrounding the MGs, the SGs and the metal gate of the logic FETs, theILD planarized to have a top surface substantially co-planar with thetop surfaces of the MGs, the SGs and the metal gate of the logic FETs.39. The semiconductor device of claim 35 wherein the charge trappinglayer in each split gate memory cell is a multi-layer charge trappinglayer comprising an oxide-nitride-oxide (ONO) stack, and wherein a loweroxide of the ONO stack is formed from an oxide layer that is contiguouswith the SG oxide layer.
 40. The semiconductor device of claim 35wherein the control circuitry comprises row and column decoders, senseamplifiers and word line or bit line drivers used to the addressplurality of split-gate devices in the memory array.